301467-005 Datasheet, PDF (228/426 Pages) Intel Corporation – Express Chipset

Functional Description
R
12.3.1.2 System Memory Supported Configurations
The (G)MCH supports the 256-Mbit, 512-Mbit and 1-Gbit technology based DIMMs from
Table 12-3.
Table 12-3. DDR / DDR2 DIMM Supported Configurations
Technology
256Mbit
256Mbit
512Mbit
512Mbit
512Mbit
1Gbit
1Gbit
1Gbit
1Gbit
Configuration
16M X 16
32M X 8
32M X 16
64M X 8
64M X 8
64M X 16
128M X 8
64M X 16
128M X 8
# of
Row
Address
Bits
13
13
13
13
14
14
14
13
14
# of Column
Address Bits
9
10
10
11
10
10
11
10
10
# of Bank
Address
Bits
2
2
2
2
2
2
2
3
3
Page
Size
Rank
Size
4K
128 MB
8K
256 MB
8K
256 MB
16K
512 MB
8K
512 MB
8K
512 MB
16K
1 GB
8K
512 MB
8K
1 GB
12.3.1.3
Main Memory DRAM Address Translation and Decoding
Table 12-4 and Table 12-5 specify the host interface to memory interface address multiplex for
the (G)MCH. Refer to the details of the various DIMM configurations as described in Table 12-3.
The address lines specified in the column header refer to the host (processor) address lines.
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Datasheet