301467-005 Datasheet, PDF (8/426 Pages) Intel Corporation – Express Chipset

R
10.1.17 MCAPPTR—Mirror of Dev0 Capability Pointer (D2:F1)
(Mirrored_D0_34) ............................................................................... 200
10.1.18 MCAPID—Mirror of Dev0 Capability Identification (D2:F1)
(Mirrored_D0_E0) ............................................................................... 200
10.1.19 MGGC—Mirror of Dev0 GMCH Graphics Control (D2:F1)
(Mirrored_D0_52) ............................................................................... 200
10.1.20 MDEVENdev0f0—Mirror of Dev0 Device Enable (D2:F1)
(Mirrored_D0_54) ............................................................................... 201
10.1.21 BSM—Base of Stolen Memory Register (D2:F1) ............................... 201
10.1.22 PMCAPID—Power Management Capabilities ID (D2:F1).................. 201
10.1.23 PMCAP—Power Management Capabilities (D2:F1) .......................... 201
10.1.24 PMCS—Power Management Control/Status (D2:F1) ........................ 202
10.1.25 SWSMI—Software SMI (D2:F1) ......................................................... 202
10.1.26 ASLS—ASL Storage (D2:F1) ............................................................. 203
10.2 Device 2 – PCI I/O Registers ............................................................................. 204
10.2.1 MMIO_INDEX—MMIO Address Register........................................... 204
10.2.2 MMIO_DATA—MMIO Data Register .................................................. 204
11
System Address Map ...................................................................................................... 205
11.1 Legacy Address Range ...................................................................................... 207
11.1.1 DOS Range (0h – 9_FFFFh) .............................................................. 208
11.1.2 Legacy Video Area (A_0000h–B_FFFFh) .......................................... 208
11.1.3 Expansion Area (C_0000h–D_FFFFh)............................................... 209
11.1.4 Extended System BIOS Area (E_0000h–E_FFFFh) .......................... 210
11.1.5 System BIOS Area (F_0000h–F_FFFFh)........................................... 210
11.1.6 Programmable Attribute Map (PAM) Memory Area Details................ 210
11.2 Main Memory Address Range (1 MB to TOLUD) .............................................. 211
11.2.1 ISA Hole (15 MB–16 MB) ................................................................... 211
11.2.2 TSEG .................................................................................................. 212
11.2.3 Pre-allocated Memory......................................................................... 212
11.3 PCI Memory Address Range (TOLUD – 4 GB) ................................................. 212
11.3.1 APIC Configuration Space (FEC0_0000h-FECF_FFFFh) ................. 214
11.3.2 HSEG (FEDA_0000h–FEDB_FFFFh) ................................................ 214
11.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................ 214
11.3.4 High BIOS Area .................................................................................. 214
11.3.5 PCI Express* Configuration Address Space (Intel^® 82915G/82915P
Only) ................................................................................................... 215
11.3.6 PCI Express* Graphics Attach (Intel^® 82915G/82915P Only)............ 215
11.3.7 AGP DRAM Graphics Aperture .......................................................... 215
11.3.8 Graphics Memory Address Ranges (Intel^®
82915G/82915GV/82915GL/82910GL GMCH Only) ......................... 216
11.4 System Management Mode (SMM) ................................................................... 216
11.4.1 SMM Space Definition ........................................................................ 217
11.4.2 SMM Space Restrictions .................................................................... 217
11.4.3 SMM Space Combinations ................................................................. 218
11.4.4 SMM Control Combinations................................................................ 218
11.4.5 SMM Space Decode and Transaction Handling ................................ 219
11.4.6 Processor WB Transaction to an Enabled SMM Address Space ...... 219
11.4.7 SMM Access through GTT TLB (Intel^® 82915G/82915GV/82910GL
GMCH Only) ....................................................................................... 219
11.4.8 Memory Shadowing ............................................................................ 219
11.4.9 I/O Address Space.............................................................................. 220
8
Datasheet