301467-005 Datasheet, PDF (88/426 Pages) Intel Corporation – Express Chipset

Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.25
LAC—Legacy Access Control (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
97h
00h
R/W
8 bits
This 8-bit register controls a fixed DRAM hole from 15–16 MB.
Bit Access &
Default
Description
7
R/W
Hole Enable (HEN): This field enables a memory hole in DRAM space. The DRAM
0b
that lies "behind" this space is not remapped.
0 = No memory hole.
1 = Memory hole from 15 MB to 16 MB.
6:1
Reserved
0
R/W
MDA Present (MDAP): This bit works with the VGA Enable bits in the BCTRL
0b
register of Device 1 to control the routing of processor initiated transactions targeting
MDA compatible I/O and memory address ranges. This bit should not be set if
device 1's VGA Enable bit is not set.
If device 1's VGA enable bit is not set, then accesses to I/O address range x3BCh–
x3BFh are forwarded to the DMI.
If the VGA enable bit is set and MDA is not present, then accesses to I/O address
range x3BCh–x3BFh are forwarded to PCI Express* if the address is within the
corresponding IOBASE and IOLIMIT, otherwise they are forwarded to the DMI.
MDA resources are defined as the following:
Memory: 0B0000h – 0B7FFFh
I/O:
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(Including ISA address aliases, A [15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be
forwarded to the DMI even if the reference includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGAEN MDAP
Description
0
0
All References to MDA and VGA space are routed to
the DMI
0
1
Illegal combination
1
0
All VGA and MDA references are routed to PCI
Express Graphics Attach.
1
1
All VGA references are routed to PCI Express
Graphics Attach. MDA references are routed to the
DMI
88
Datasheet