301467-005 Datasheet, PDF (62/426 Pages) Intel Corporation – Express Chipset

Register Description
R
3.3.5 Intel^® 915x GMCH Configuration Cycle Flowchart
Figure 3-6. Intel^® 915x GMCH Configuration Cycle Flowchart
DW I/O Write to
CONFIG_ADDRES
S with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
Yes
Bus# = 0
No
GMCH Generates
Type 1 Access to
PCI Express
Bus# > Sec Bus
Yes _{Bus# ≤ Sub Bus}
in GMCH Dev 1
No
Bus# =
Yes Secondary Bus in
GMCH Dev 1
No
GMCH Generates MISI
Type 1Configuration
Cycle
Device# = 0
No
Yes
GMCH Claims if
Function# = 0
Device# = 1 &
Yes
GMCH Claims if
Dev # 1 Enabled
Function# = 0
No
Device# = 2 &
Dev# 2
Enabled
Yes
GMCH Claims if
Function# = 0
No
Device# = 0
No
MCH allows cycle to
go to DMI resulting in
Master Abort
Yes
GMCH Generates
Type 0 Accessto
PCI Express
Device# = 7&
Yes
Dev# 7 Enabled
No
GMCH Generates DMI
Type 0 Configuration
Cycle
GMCH Claims if
Function# = 0
Config_Cyc_Flow_915
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Datasheet