301467-005 Datasheet, PDF (31/426 Pages) Intel Corporation – Express Chipset

Introduction
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1.3.6
1.3.7
1.3.8
Analog and Intel^® SDVO Displays (Intel^®
82915G/82915GV/82910GL/82915GL GMCH Only)
The GMCH provides interfaces to a progressive scan analog monitor and two SDVO ports
(multiplexed with PCI Express x16 Graphics Port signals) capable of driving an ADD2 card. The
digital display channels are capable of driving a variety of SDVO devices (e.g., TMDS, TV-Out).
Note that SDVO only works with the Integrated Graphics Device (IGD). The GMCH provides
two SDVO ports that are capable of driving up to a 200 MHz pixel clock each.
The GMCH SDVO ports can each support a single-channel SDVO device. If both ports are active
in single-channel mode, they can have different display timing and data. Alternatively, the SDVO
ports can combine to support dual channel devices, supporting higher resolutions and refresh
rates. The GMCH is compliant with DVI Specification 1.0. When combined with a DVI
compliant external device and connector, the GMCH has a high-speed interface to a digital
display (e.g., flat panel or digital CRT).
The GMCH Supports Hot-Plug and Display for PCI Express* x16 Graphics. This is not supported
for ADD2 cards.
System Interrupts
The (G)MCH interrupt support includes:
• Supports both 8259 and Pentium 4 processor FSB interrupt delivery mechanisms.
• Supports interrupts signaled as upstream Memory Writes from PCI Express and DMI
⎯ MSIs routed directly to FSB
⎯ From I/OxAPICs
(G)MCH Clocking
The differential FSB clock (HCLKP/HCLKN) can be set to either 133 MHz or 200 MHz
(82915G/82915GV/82915GL/82915P/82915PL only). This supports FSB transfer rates of 533
MT/s and 800 MT/s (82915G/82915GV/82915GL/82915P/82915PL only). The Host PLL
generates 2X, 4X, and 8X versions of the host clock for internal optimizations. The (G)MCH core
clock is synchronized to the host clock.
The internal and external memory clocks of 133 MHz and 200 MHz are generated from one of
two (G)MCH PLLs that use the host clock as a reference. This includes 2X and 4X for internal
optimizations.
For the 82915G/82915P/82915PL (G)MCH, the PCI Express core clock of 250 MHz is generated
from a separate PCI Express PLL. This clock uses the fixed 100 MHz Serial Reference Clock
(GCLKP/GCLKN) for reference.
For the 82915G/82915GV/82915GL/82910GL GMCH, display timings are generated from
display PLLs that use a 96 MHz differential non-spread spectrum clock as a reference. Display
PLLs can also use the SDVO_TVCLKIN[+/-] from an SDVO device as a reference.
Datasheet
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