301467-005 Datasheet, PDF (181/426 Pages) Intel Corporation – Express Chipset

Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.11
IOBAR—I/O Base Address (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
14h
00000001h
RO, R/W
32 bits
This register provides the Base offset of the I/O registers within Device 2. Bits 15:3 are
programmable allowing the I/O Base to be located anywhere in 16 bit I/O address space. Bits 2:1
are fixed and return 0s; bit 0 is hardwired to a 1 indicating that 8 bytes of I/O space are decoded.
Access to the 8Bs of I/O space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set.
Access is disallowed in PM states D1–D3 or if IO Enable is clear or if Device 2 is turned off.
Note that access to this I/O BAR is independent of VGA functionality within Device 2. Also note
that this mechanism in available only through function 0 of Device 2 and is not duplicated in
Function 1.
If accesses to this I/O bar are allowed, the GMCH claims all 8, 16, or 32 bit I/O cycles from the
processor that falls within the 8B claimed.
Bit
31:16
15:3
2:1
0
Access &
Default
R/W
0000h
RO
00b
RO
1b
Description
Reserved
IO Base Address: Set by the OS, these bits correspond to address signals
[15:3].
Memory Type: Hardwired to 0s to indicate 32-bit address.
Memory / I/O Space: Hardwired to 1 to indicate I/O space.
Datasheet
181