301467-005 Datasheet, PDF (197/426 Pages) Intel Corporation – Express Chipset

Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.5
10.1.6
RID2—Revision Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
08h
See description below
RO
8 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
CC—Class Code Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
09h
038000h
RO
24 bits
This register contains the device programming interface information related to the Sub-Class
Code and Base Class Code definition for the IGD. This register also contains the Base Class Code
and the function sub-class in relation to the Base Class Code.
Bit
23:16
15:8
7:0
Access &
Default
RO
03h
RO
80h
RO
00h
Description
Base Class Code (BCC): This is an 8-bit value that indicates the base class
code for the GMCH.
03h = Display Controller.
Sub-Class Code (SUBCC)
80h = Non VGA
Programming Interface (PI)
00h = Hardwired as a Display controller.
10.1.7
CLS—Cache Line Size (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
0Ch
00h
RO
8 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
Datasheet
197