301467-005 Datasheet, PDF (65/426 Pages) Intel Corporation – Express Chipset

Host Bridge/DRAM Controller Registers (D0:F0)
R
4 Host Bridge/DRAM Controller
Registers (D0:F0)
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).
Warning: Address locations that are not listed are considered Reserved registers locations. Reads to
Reserved registers may return non-zero values. Writes to reserved locations may cause system
failures.
All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in
this component are not included in this document. The reserved/unimplemented space in the PCI
configuration header space is not documented as such in this summary.
Table 4-1. Device 0 Function 0 Register Address Map Summary
Address
Offset
00–01h
02–03h
04–05h
06–07h
08h
09–0Bh
0Ch
0Dh
0Eh
0F–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
35–3Fh
40–43h
44–47h
48–4Bh
4C–4Fh
Register
Symbol
VID
DID
PCICMD
PCISTS
RID
CC
—
MLT
HDR
—
SVID
SID
—
CAPPTR
—
EPBAR
MCHBAR
PCIEXBAR
DMIBAR
Register Name
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Reserved
Master Latency Timer
Header Type
Reserved
Subsystem Vendor Identification
Subsystem Identification
Reserved
Capabilities Pointer
Reserved
Egress Port Base Address
GMCH Memory Mapped Register Range
Base Address
PCI Express* Register Range Base Address
Root Complex Register Range Base
Address
Default
Value
8086h
2580h
0006h
0090h
See register
description
060000h
—
00h
00h
—
0000h
0000h
—
EOh
—
00000000h
00000000h
E0000000h
00000000h
Access
RO
RO
RO, R/W
RO,
R/W/C
RO
RO
—
RO
RO
—
R/W/O
R/W/O
—
RO
—
RO
R/W
R/W
R/W
Datasheet
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