301467-005 Datasheet, PDF (400/426 Pages) Intel Corporation – Express Chipset

Testability
R
15.2
XOR Test Mode Initialization for DDR
XOR test mode (DDR) can be entered by pulling the reserved ballout RSV (located at F15) low
through the de-assertion of external reset (RSTIN#). It was intended that no clocks should be
required to enter this test mode; however, it is recommended that customers used the following
sequence.
On power up, hold PWROK, PCIRST#, and reserved ballout RSV (located at F15) low and start
external clocks, refer to the timing diagram below. After a few clock cycles, pull PWROK high.
After ~3–4 clocks, de-assert PCIRST# (pull it high). Release reserved ballout RSV (located at
F15). No external drive. Allow the clocks to run for an additional 32 clocks. Begin testing the
XOR chains. Refer to timing diagram in below.
15.3 XOR Test Mode Initialization for DDR2
XOR test mode (DDR2) can be entered by pulling reserved ballout RSV(located at F15) and
MTYPE low through the de-assertion of external reset (RSTIN#). It was intended that no clocks
should be required to enter this test mode; however, it is recommended that customers use the
following sequence.
On power up, hold PWROK, PCIRST#, and reserved ballout RSV (located at F15) low and start
external clocks. After a few clock cycles, pull PWROK high. After ~3-4 clocks, de-assert
PCIRST# (pull it high). Release reserved ballout RSV (located at F15) and MTYPE. No external
drive. Allow the clocks to run for an additional 32 clocks. Begin testing the XOR chains. Refer to
Figure 15-1.
Figure 15-1. XOR Test Mode Initialization Cycles
32 clocks
PWROK
RSV_F15
~3-4 Clocks
Don’t Care
MTYPE
1 if DDR1; 0 if DDR2
Don’t Care
RSTIN#
Start XOR testing
XOR_Chain_Tim
400
Datasheet