301467-005 Datasheet, PDF (202/426 Pages) Intel Corporation – Express Chipset

Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.24
PMCS—Power Management Control/Status (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
D4h
0000h
RO, R/W
16 bits
Bit
Access &
Default
Description
15
RO
PME_Status: This bit is 0 to indicate that IGD does not support PME# generation
0b
from D3 (cold).
14:9
Reserved
8
RO
PME_En: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
0b
7:2
Reserved
1:0
R/W
Power State: This field indicates the current power state of the IGD and can be
00 b
used to set the IGD into a new power state. If software attempts to write an
unsupported state to this field, write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
On a transition from D3 to D0 the graphics controller is optionally reset to initial
values. Behavior of the graphics controller in supported states is detailed in the
power management section.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
10.1.25
SWSMI—Software SMI (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
E0h
0000h
R/W
16 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
202
Datasheet