301467-005 Datasheet, PDF (226/426 Pages) Intel Corporation – Express Chipset

Functional Description
R
12.3
System Memory Configuration Registers Overview
The configuration registers located in the PCI configuration space of the (G)MCH control the
system memory operation. Following is a brief description of configuration registers.
• DRAM Rank Boundary (CxDRBy): The x represents a channel, either A (where x = 0) or
B (where x = 1). The y represents a rank, 0 through 3. DRB registers define the upper
addresses for a rank of DRAM devices in a channel. When the (G)MCH is configured in
asymmetric mode, each register represents a single rank. When the (G)MCH is configured in
a dual interleaved mode, each register represents a pair of corresponding ranks in opposing
channels. There are 4 DRB registers for each channel.
• DRAM Rank Architecture (CxDRAy): The x represents a channel, either A (where x = 0)
or B (where x = 1). The y represents a rank, 0 through 3. DRA registers specify the
architecture features of each rank of devices in a channel. The only architecture feature
specified is page size. When the (G)MCH is configured in asymmetric mode, each DRA
represents a single rank in a single channel. When the (G)MCH is configured in a dual-
channel lock-step or interleaved mode, each DRA represents a pair of corresponding ranks in
opposing channels. There are 4 DRA registers per channel. Each requires only 3 bits, so there
are two DRAs packed into a byte.
• Clock Configuration (CLKCFG): Specifies DRAM frequency. The same clock frequency
will be driven to all DIMMs.
• DRAM Timing (CxDRTy): The x represents a channel, A (where x = 0) or B
(where x = 1). A second register for a channel is differentiated by y, A or B. The DRT
registers define the timing parameters for all devices in a channel. The BIOS programs this
register with “least common denominator” values after reading the SPD registers of each
DIMM in the channel.
• DRAM Control (CxDRCy): The x represents a channel, A (where x = 0) or B
(where x = 1). A second register for a channel is differentiated by y, A or B. DRAM refresh
mode, rate, and other controls are selected here.
226
Datasheet