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301467-005 Datasheet, PDF (264/426 Pages) Intel Corporation – Express Chipset
Electrical Characteristics
R
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes
1.5 V PCI Express Interface 1.0a (includes PCI Express and SDVO)
VTX-DIFF P-P
VTX_CM-ACp
ZTX-DIFF-DC
VRX-DIFF p-p
VRX_CM-ACp
(f) Differential Peak to Peak
0.400
—
0.600
V
2
Output Voltage
(f) AC Peak Common Mode
—
—
20
mV
Output Voltage
(f) DC Differential TX
Impedance
80
100
120
Ohms
(e) Differential Peak to Peak
0.175
—
0.600
V
3
Input Voltage
(e) AC peak Common Mode
—
—
150
mV
Input Voltage
Clocks, Reset, and Miscellaneous Signals
VIL
VIH
ILEAK
CIN
VIL
VIH
VCROSS
VOL
VOH
IOL
IOH
VIL
VIH
ILEAK
CIN
VIL
VIH
ILEAK
CIN
(n) Input Low Voltage
(n) Input High Voltage
(n) Input Leakage Current
(n) Input Capacitance
(o) Input Low Voltage
(o) Input High Voltage
(o) Crossing Voltage
(p) Output Low Voltage (CMOS
Outputs)
(p) Output High Voltage (CMOS
Outputs)
(p) Output Low Current (CMOS
Outputs)
(p) Output High Current (CMOS
Outputs)
(p) Input Low Voltage
(p) Input High Voltage
(p) Crossing Voltage
(p) Input Capacitance
(n1) Input Low Voltage
(n1) Input High Voltage
(n1) Crossing Voltage
(n1) Input Capacitance
—
2.0
—
3.0
—
0.660
0.45 x (VIH –
VIL)
—
2.1
—
-1
—
1.4
—
3.0
—
2.0
—
4.690
—
—
—
—
0
0.710
0.5 x
(VIH – VIL)
—
—
—
—
—
—
—
—
—
—
—
—
0.8
—
±10
6.0
—
0.850
0.55 x (VIH –
VIL)
0.4
—
1
—
1.1
—
±10
6.0
0.8
—
±100
5.370
V
V
µA
pF
V
V
V
V
V
mA @VOL_HI max
mA @VOH_HI min
V
V
µA
pF
V
V
µA 0<Vin<VCC3_3
pF
NOTES:
1. Determined with 2x (G)MCH DDR/DDR2 Buffer Strength Settings into a 50 Ω to 0.5xVCCSM
(DDR/DDR2) test load.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in
Transmitter compliance eye diagram of PCI-E specification and measured over any 250 consecutive TX
Uls.
3. Specified at the measurement point and measured over any 250 consecutive Uls. The test load shown
in Receiver compliance eye diagram of PCI-E specification should be used as the RX device when
taking measurements.
264
Datasheet