301467-005 Datasheet, PDF (3/426 Pages) Intel Corporation – Express Chipset

R
Contents
1
Introduction ....................................................................................................................... 17
1.1 Terminology.......................................................................................................... 24
1.2 Reference Documents.......................................................................................... 26
1.3 GMCH (MCH) Overview....................................................................................... 26
1.3.1 Host Interface........................................................................................ 26
1.3.2 System Memory Interface..................................................................... 27
1.3.3 Direct Media Interface (DMI)................................................................. 28
1.3.4 PCI Express* Graphics Interface (Intel^® 82915G/82915P/
and 82915PL Only) ............................................................................... 28
1.3.5 Integrated Graphics (Intel^® 82915G/82915GV/82910GL/82915GL
GMCH Only) ......................................................................................... 29
1.3.6 Analog and Intel^® SDVO Displays (Intel^®
82915G/82915GV/82910GL/82915GL GMCH Only) ........................... 31
1.3.7 System Interrupts.................................................................................. 31
1.3.8 (G)MCH Clocking.................................................................................. 31
1.3.9 Power Management.............................................................................. 32
2
Signal Description ............................................................................................................. 33
2.1 Host Interface Signals .......................................................................................... 35
2.2 DDR/DDR2 DRAM Channel A Interface .............................................................. 38
2.3 DDR/DDR2 DRAM Channel B Interface .............................................................. 39
2.4 DDR/DDR2 DRAM Reference and Compensation .............................................. 40
2.5 PCI Express* x16 Graphics Port Signals (Intel^® 82915G, 82915P,
82915PL Only)...................................................................................................... 41
2.6 Analog Display Signals (Intel^® 82915G/82915GV/82915GL/82910GL
GMCH Only) ......................................................................................................... 42
2.7 Clocks, Reset, and Miscellaneous ....................................................................... 43
2.8 Direct Media Interface (DMI) ................................................................................ 43
2.9 Intel^® Serial DVO (SDVO) Interface (82915G/82915GV/82915GL/82910GL
GMCH Only) ......................................................................................................... 44
2.10 Power and Ground ............................................................................................... 45
2.11 Reset States and Pull-up/Pull-downs................................................................... 46
3
Register Description.......................................................................................................... 53
3.1 Register Terminology ........................................................................................... 53
3.2 Platform Configuration.......................................................................................... 55
3.3 General Routing Configuration Accesses ............................................................ 58
3.3.1 Standard PCI Bus Configuration Mechanism ....................................... 58
3.3.2 Logical PCI Bus 0 Configuration Mechanism ....................................... 58
3.3.3 Primary PCI and Downstream Configuration Mechanism .................... 59
3.3.4 PCI Express* Enhanced Configuration Mechanism ............................. 60
3.3.5 Intel^® 915x GMCH Configuration Cycle Flowchart ............................... 62
3.4 I/O Mapped Registers .......................................................................................... 63
3.4.1 CONFIG_ADDRESS—Configuration Address Register ...................... 63
Datasheet
3