301467-005 Datasheet, PDF (196/426 Pages) Intel Corporation – Express Chipset

Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.4
PCISTS2—PCI Status (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
06h
0090h
RO
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and
PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the
IGD.
Bit
Access &
Default
Description
15
RO
Detected Parity Error (DPE): Since the IGD does not detect parity; this bit is
0b
always hardwired to 0.
14
RO
Signaled System Error (SSE): The IGD never asserts SERR#; therefore, this
0b
bit is hardwired to 0.
13
RO
Received Master Abort Status (RMAS): The IGD never gets a Master Abort,
0b
therefore this bit is hardwired to 0.
12
RO
Received Target Abort Status (RTAS): The IGD never gets a Target Abort,
0b
therefore this bit is hardwired to 0.
11
RO
Signaled Target Abort Status (STAS): Hardwired to 0. The IGD does not use
0b
target abort semantics.
10:9
RO
DEVSEL Timing (DEVT): These bits are hardwired to 00.
00b
8
RO
Master Data Parity Error Detected (DPD): Since Parity Error Response is
0b
hardwired to disabled (and the IGD does not do any parity detection), this bit is
hardwired to 0.
7
RO
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast back-to-back
1b
when the transactions are not to the same agent.
6
RO
User Defined Format (UDF). Hardwired to 0.
0b
5
RO
66 MHz PCI Capable (66C). Hardwired to 0.
0b
4
RO
Capability List (CLIST): This bit is set to 1 to indicate that the register at 34h
1b
provides an offset into the function’s PCI Configuration Space containing a
pointer to the location of the first item in the list.
3
RO
Interrupt Status: Hardwired to 0.
0b
2:0
Reserved
196
Datasheet