301467-005 Datasheet, PDF (112/426 Pages) Intel Corporation – Express Chipset

EPBAR Registers—Egress Port Register Summary
R
6.1.4
EPLE2D—EP Link Entry 2 Description
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
EPBAR
060h
02000002h
R/WO, RO
32 bits
This register provides the First part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
31:24
23:16
15:2
1
0
Access &
Default
Description
RO
02h
R/WO
00h
RO
1b
R/WO
0b
Target Port Number: This field specifies the port number associated with the
element targeted by this link entry (PCI Express* x16 interface). The target port
number is with respect to the component that contains this element as specified
by the target component ID.
Target Component ID: This field identifies the physical or logical component that
is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Reserved
Link Type:
1 = Link points to configuration space of the integrated device that controls the
x16 root port. The link address specifies the configuration address (segment,
bus, device, function) of the target root port.
Link Valid
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
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Datasheet