301467-005 Datasheet, PDF (51/426 Pages) Intel Corporation – Express Chipset

Signal Description
R
Table 2-6. Clocking Reset and S3 States
Interface
Signal Name
Clocks
HCLKN
HCLKP
GCLKN
GCLKP
DREFCLKN
DREFCLKP
State During
I/O
RSTIN#
Assertion
I
IN
I
IN
I
IN
I
IN
I
IN
I
IN
State After
RSTIN# De-
assertion
IN
IN
IN
IN
IN
IN
S3
Pull-up/
Pull-down
IN
IN
IN
IN
IN
IN
Table 2-7. MISC Reset and S3 States
Interface
Signal Name
Misc.
RSTIN#
PWROK
EXTTS#
BSEL[2:0]
MTYPE
EXP_SLR
ICH_SYNC#
SDVO_CTRLCLK
SDVO_CTRLDATA
I/O
State During
RSTIN#
Assertion
State After RSTIN#
De-assertion
I
IN
I
HV
I
PU
I
TRI
I
TERM HV
I
TERM HV
O
PU
O
TRI
I/O
TERM PD
IN
HV
PU
TRI
TERM HV
TERM HV
PU
TRI
TRI
S3
IN
HV
PU
TRI
TERM HV
TERM HV
PU
TRI
TERM PD
Pull-up/
Pull-down
Table 2-8. DAC Reset and S3 States (Intel^® 82915G/82915GV/82915GL/82910GL GMCH only)
Interface
Signal Name
I/O
State During
RSTIN#
Assertion
State After RSTIN#
Deassertion
S3
DAC
HSYNC
VSYNC
RED
RED#
GREEN
GREEN#
BLUE
BLUE#
REFSET
O
LV
LV
O
LV
LV
O
TRI
TRI
TRI
O
TRI
TRI
TRI
O
TRI
TRI
TRI
O
TRI
TRI
TRI
O
TRI
TRI
TRI
O
TRI
TRI
TRI
O
TRI
0.5* VCCA_DAC
TRI
DDC_CLK
I/O
IN
IN
IN
DDC_DATA
I/O
IN
IN
IN
Pull-up/
Pull-down
255 Ω 1%
Resistor to
Ground
§
Datasheet
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