301467-005 Datasheet, PDF (179/426 Pages) Intel Corporation – Express Chipset

Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.7
9.1.8
CLS—Cache Line Size (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
0Ch
00h
RO
8 bits
The IGD does not support this register as a PCI slave.
Bit
Access &
Default
Description
7:0
RO
Cache Line Size (CLS): This field is hardwired to 0s. The IGD, as a PCI
00h
compliant master, does not use the Memory Write and Invalidate command and,
in general, does not perform operations based on cache line size.
MLT2—Master Latency Timer (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
0Dh
00h
RO
8 bits
The IGD does not support the programmability of the master latency timer because it does not
perform bursts.
Bit
Access &
Default
Description
7:0
RO
Master Latency Timer Count Value: Hardwired to 0s.
00h
Datasheet
179