301467-005 Datasheet, PDF (166/426 Pages) Intel Corporation – Express Chipset

Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.51
VC0RSTS—VC0 Resource Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
11Ah
0000h
RO
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
Description
15:2
Reserved
1
RO
VC0 Negotiation Pending
1b
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
This bit indicates the status of the process of Flow Control initialization. It is set by
default on Reset, as well as whenever the corresponding Virtual Channel is
Disabled or the Link is in the DL_Down state. It is cleared when the link
successfully exits the FC_INIT2 state
Before using a Virtual Channel, software must check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in both Components on a Link.
0
Reserved
8.1.52
VC1RCAP—VC1 Resource Capability (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
11Ch
00008000h
RO
32 bits
Bit
31:16
15
14:0
Access &
Default
Description
Reserved
RO
Reject Snoop Transactions
1b
0 = Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP header will be
rejected as an Unsupported Request.
Reserved
166
Datasheet