301467-005 Datasheet, PDF (83/426 Pages) Intel Corporation – Express Chipset

Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.20
PAM2—Programmable Attribute Map 2 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
92h
00h
R/W
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h–
0CFFFFh.
Bit Access &
Default
Description
7:6
Reserved
5:4
R/W
0CC000h–0CFFFFh Attribute (HIENABLE):
00b
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
3:2
Reserved
1:0
R/W
0C8000h–0CBFFFh Attribute (LOENABLE): This field controls the steering of read
00b
and write cycles that address the BIOS area from 0C8000h to 0CBFFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Datasheet
83