301467-005 Datasheet, PDF (259/426 Pages) Intel Corporation – Express Chipset

Electrical Characteristics
R
13.3 Signal Groups
The signal description includes the type of buffer used for the particular signal:
GTL+
Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification
for complete details. The (G)MCH integrates most GTL+ termination
resistors.
DDR
DDR System memory (2.6 V CMOS buffers)
DDR2
DDR2 System memory (1.8 V CMOS buffers)
PCI Express/SDVO PCI Express interface signals. These signals are compatible with PCI
Express 1.0a signaling environment AC Specifications. The buffers are
not 3.3 V tolerant.
Analog
Analog signal interface
Ref
Voltage reference signal
HVCMOS
2.5 V Tolerant High Voltage CMOS buffers
SSTL-2
2.6 V Tolerant Stub Series Termination Logic
SSTL-1.8
1.8 V Tolerant Stub Series Termination Logic
Table 13-5. Signal Groups
Signal
Group
Signal Type
Signals
Notes
Host Interface Signal Groups
(a)
GTL+
HADS#, HBNR#, HBREQ0#, HDBSY#, HDRDY#,
Input/Outputs HDINV[3:0]#, HA[31:3]#, HADSTB[1:0]#, HD[63:0],
HDSTBP[3:0]#, HDSTBN[3:0]#, HHIT#, HHITM#,
HREQ[4:0]#, HLOCK#
(b)
GTL+
HBPRI#, HCPURST#, HDEFER#, HTRDY#, HRS[2:0]#,
Common Clock HDPWR#, HEDRDY#
Outputs
(c)
GTL+
BSEL[2:0], HPCREQ#
Asynchronous
Input
(d)
Analog Host I/F HVREF, HSWING HRCOMP, HSCOMP
Ref & Comp.
Signals
PCI-Express Graphics and SDVO Interface Signal Groups
(e)
PCI
PCI Express Interface (82915G/82915P/82915PL
Express/SDVO (G)MCH only): EXP_RXN[15:0], EXP_RXP[15:0],
Input
SDVO Interface (82915G/82915GV/82915GL/82910GL
GMCH only): SDVO_TVCLKIN#, SDVO_TVCLKIN,
SDVOB_INT#, SDVOB_INT, SDVO_STALL#,
SDVO_STALL, SDVOC_INT#, SDVOC_INT
Datasheet
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