301467-005 Datasheet, PDF (200/426 Pages) Intel Corporation – Express Chipset

Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.15
MINGNT—Minimum Grant Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
3Eh
00h
RO
8 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.16
MAXLAT—Maximum Latency (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
3Fh
00h
RO
8 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.17
MCAPPTR—Mirror of Dev0 Capability Pointer (D2:F1)
(Mirrored_D0_34)
PCI Device:
Function:
Address Offset:
Size:
2
1
44h
8 bits
This register is a Read Only copy of Device 0, Offset 34h register.
10.1.18
MCAPID—Mirror of Dev0 Capability Identification (D2:F1)
(Mirrored_D0_E0)
PCI Device:
Function:
Address Offset:
Size:
2
1
48h
72 bits
This register is a Read-Only copy of Device 0, Offset E0h register.
10.1.19
MGGC—Mirror of Dev0 GMCH Graphics Control (D2:F1)
(Mirrored_D0_52)
PCI Device:
Address Offset:
Size:
2
52h
16 bits
This register is a Read Only copy of Device 0, Offset 52h register.
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