301467-005 Datasheet, PDF (225/426 Pages) Intel Corporation – Express Chipset

Functional Description
R
Figure 12-1. System Memory Styles
Single Channel
Dual Channel Interleaved
(channels do not have to
match)
Dual Channel Asymmetric
(channels do not have to
match)
CL
CL
TOM
CH B
TOM
CH A
CH A or CH B
CH B
CH A
CH B
CH A
0
0
Scheme
XOR Bit 6 => CL
CL
CH B
CH B
TOM
CH B0
CH A
TOM
CH A
CH A0
Sys_Mem_Styles
Table 12-1. Sample System Memory Organization with Interleaved Channels
Rank
3
2
1
0
Channel A
population
0 MB
256 MB
512 MB
512 MB
Cumulative
top address in
Channel A
2560 MB
2560 MB
2048 MB
1024 MB
Channel B
population
0 MB
256 MB
512 MB
512 MB
Cumulative
top address in
Channel B
2560 MB
2560 MB
2048 MB
1024 MB
Table 12-2. Sample System Memory Organization with Asymmetric Channels
Rank
3
2
1
0
Channel A
population
0 MB
256 MB
512 MB
512 MB
Cumulative
top address in
Channel A
1280 MB
1280 MB
1024 MB
512 MB
Channel B
population
0 MB
256 MB
512 MB
512 MB
Cumulative
top address in
Channel B
2560 MB
2560 MB
2304 MB
1792 MB
Datasheet
225