301467-005 Datasheet, PDF (61/426 Pages) Intel Corporation – Express Chipset

Register Description
R
To access this space (steps 1, 2, 3 are performed only once by BIOS)
1. Use the PCI compatible configuration mechanism to enable the PCI Express enhanced
configuration mechanism by writing 1 to bit 31 of the DEVEN register.
2. Use the PCI compatible configuration mechanism to write an appropriate PCI Express base
address into the PCIEXBAR register.
3. Calculate the host address of the register you wish to set using (PCI Express base + (bus
number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) + (1 B * offset
within the function) = host address).
4. Use a memory write or memory read cycle to the calculated host address to write to or read
from that register.
31 28 27
Base
Bus
20 19
15 14 12 11 8 7
210
Device
Function Extended
Register
Number
XX
Config_Write
PCI Express Configuration Writes
Internally the host interface unit translates writes to PCI Express extended configuration space to
configurations on the backbone. Writes to extended space are posted on the FSB, but non-posted
on the PCI Express* x16 Graphics Interface or DMI pins (i.e., translated to configuration writes).
See the PCI Express Specification for more information on both the PCI 2.3 compatible and PCI
Express enhanced configuration mechanism and transaction rules.
Datasheet
61