301467-005 Datasheet, PDF (195/426 Pages) Intel Corporation – Express Chipset

Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.3
PCICMD2—PCI Command (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
04h
0000h
RO, R/W
16 bits
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The
PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Access &
Default
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
R/W
0b
R/W
0b
R/W
0b
Description
Reserved
Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.
SERR Enable (SERRE): Not Implemented. Hardwired to 0.
Address/Data Stepping Enable (ADSTEP): Not Implemented. Hardwired to 0.
Parity Error Enable (PERRE): Not Implemented. Hardwired to 0. Since the IGD
belongs to the category of devices that does not corrupt programs or data in
system memory or hard drives, the IGD ignores any parity error that it detects
and continues with normal operation.
VGA Palette Snoop Enable (VGASNOOP): This bit is hardwired to 0 to disable
snooping.
Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The IGD does
not support memory write and invalidate commands.
Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD ignores Special
cycles.
Bus Master Enable (BME):
0 = Disable
1 = Enable the IGD to function as a PCI compliant master.
Memory Access Enable (MAE): This bit controls the IGD’s response to memory
space accesses.
0 = Disable.
1 = Enable.
I/O Access Enable (IOAE): This bit controls the IGD’s response to I/O space
accesses.
0 = Disable.
1 = Enable.
Datasheet
195