301467-005 Datasheet, PDF (215/426 Pages) Intel Corporation – Express Chipset

System Address Map
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11.3.5 PCI Express* Configuration Address Space (Intel^®
82915G/82915P Only)
A configuration register defines the base address for the 256-MB block of addresses below top of
addressable memory (4 GB) for the configuration space associated with all devices and functions
that are potentially a part of the PCI Express root complex hierarchy. This range will be aligned to
a 256-MB boundary. BIOS must assign this address range such that it will not conflict with any
other address ranges.
11.3.6 PCI Express* Graphics Attach (Intel^® 82915G/82915P Only)
The (G)MCH can be programmed to direct memory accesses to the PCI Express interface when
addresses are within either of two programmed ranges specified via registers in the (G)MCH’s
Device 1 configuration space.
• The first range is controlled via the Memory Base Register (MBASE) and Memory Limit
Register (MLIMIT) registers.
• The second range is controlled via the Prefetchable Memory Base (PMBASE) and
Prefetchable Memory Limit (PMLIMIT) registers.
The (G)MCH positively decodes memory accesses to PCI Express memory address space as
defined by the following equations:
Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
Prefetchable_Memory_Base_Address ≤ Address ≤
Prefetchable_Memory_Limit_Address
It is essential to support a separate Prefetchable range to apply USWC attribute (from the
processor point of view) to that range. The USWC attribute is used by the processor for write
combining.
Note: The programmable ranges are used to allocate memory address space for any PCI Express devices
sitting on PCI Express that require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In other
words, the memory access enable bit must be set in the device 1 PCICMD1 register to enable the
memory base/limit and prefetchable base/limit windows.
11.3.7
AGP DRAM Graphics Aperture
Unlike AGP4x, PCI Express has no concept of aperture for PCI Express devices. As a result,
there is no need to translate addresses from PCI Express. Therefore, the (G)MCH has no
APBASE and APSIZE registers.
Datasheet
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