301467-005 Datasheet, PDF (103/426 Pages) Intel Corporation – Express Chipset

MCHBAR Registers
R
Bit
Access &
Default
Description
6:4
R/W
DRAM RAS to CAS Delay (t_RCD). This bit controls the number of clocks inserted
010b
between a row activate command and a read or write command to that row.
000 = 2 DRAM clocks
001 = 3 DRAM clocks
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
3
Reserved
2:0
R/W
DRAM RAS Precharge (t_RP). This bit controls the number of clocks that are
010b
inserted between a row precharge command and an activate command to the
same rank.
000 = 2 DRAM clocks
001 = 3 DRAM clocks
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
Datasheet
103