301467-005 Datasheet, PDF (188/426 Pages) Intel Corporation – Express Chipset

Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.27
MSAC—Multi Size Aperture Control (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
62h
00h
R/W
8 bits
This register determines the size of the graphics memory aperture in function 0 and in the trusted
space. By default, the aperture size is 256 MB (bit 27 read only). If bit 1 is set to a 1, then the
aperture size is limited to 128 MB. Only the system BIOS will write this register based on pre-
boot address allocation efforts, but the graphics may read this register to determine the correct
aperture size. System BIOS needs to save this value on boot so that it can reset it correctly during
S3 resume.
Bit Access &
Default
Description
7:4
R/W
Scratch Bits Only. These bits have no physical effect on hardware.
0h
3:2
Reserved
1
R/W
256-MB Aperture Disable
0b
0 = Bit 27 of GMADR and the equivalent trusted memory aperture is read-only,
allowing 256 MB of address space to be mapped.
1 = Bit 27 of GMADR and the equivalent trusted memory aperture is read-write,
limiting the address space to 128 MB.
0
Reserved
9.1.28
PMCAPID—Power Management Capabilities ID (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
D0h
0001h
RO
16 bits
Bit
Access &
Default
Description
15:8
RO
NEXT_PTR: This field contains a pointer to next item in capabilities list. This is
00h
the final capability in the list and must be set to 00h.
7:0
RO
CAP_ID: SIG defines this ID is 01h for power management.
01h
188
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