301467-005 Datasheet, PDF (58/426 Pages) Intel Corporation – Express Chipset

Register Description
R
3.3
3.3.1
3.3.2
General Routing Configuration Accesses
The (G)MCH supports two PCI related interfaces: DMI and PCI Express. PCI and PCI Express
configuration cycles are selectively routed to one of these interfaces. The (G)MCH is responsible
for routing configuration cycles to the proper interface. Configuration cycles to the Intel ICH6
internal devices and Primary PCI (including downstream devices) are routed to the Intel ICH6 via
DMI. Configuration cycles to both the PCI Express Graphics PCI compatibility configuration
space and the PCI Express Graphics extended configuration space are routed to the PCI Express
Graphics port.
A detailed description of the mechanism for translating processor I/O bus cycles to configuration
cycles is described below.
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI
specification defines two bus cycles to access the PCI configuration space: Configuration Read
and Configuration Write. Memory and I/O spaces are supported directly by the processor.
Configuration space is supported by a mapping mechanism implemented within the (G)MCH.
The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O
address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh though
0CFFh). To reference a configuration register a DW I/O write cycle is used to place a value into
CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the
device, and a specific configuration register of the device function being accessed.
CONFIG_ADDRESS [31] must be 1 to enable a configuration cycle. CONFIG_DATA then
becomes a window into the four bytes of configuration space specified by the contents of
CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the (G)MCH
translating the CONFIG_ADDRESS into the appropriate configuration cycle.
The (G)MCH is responsible for translating and routing the processor’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal (G)MCH configuration registers,
DMI or PCI Express.
Logical PCI Bus 0 Configuration Mechanism
The (G)MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus 0 device. The Host-DMI Bridge entity within the
(G)MCH is hardwired as Device 0 on PCI Bus 0. The Host-PCI Express Bridge entity within the
(G)MCH is hardwired as Device 1 on PCI Bus 0. The 82915G/82915GV/82915GL/82910GL
GMCH’s Device 2 contains the control registers for the Integrated Graphics Controller. The Intel
ICH6 decodes the Type 0 access and generates a configuration access to the selected internal
device.
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Datasheet