301467-005 Datasheet, PDF (194/426 Pages) Intel Corporation – Express Chipset

Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
Address
Offset
48–50h
51h
52–53h
54–57h
58–5Bh
5C–5Fh
60–CFh
D0–D1h
D2–D3h
D4–D5h
D6–DFh
E0–E1h
E2–FBh
FC–FFh
Register
Symbol
MCAPID
—
MGGC
MDEVENdev0f0
—
BSM
—
PMCAPID
PMCAP
PMCS
—
SWSMI
—
ASLS
Register Name
Mirror of Dev0 Capability Identification
Reserved
Mirror of Dev0 GMCH Graphics Control
Mirror of Dev0 Device Enable
Reserved
Base of Stolen Memory Register
Reserved
Power Management Capabilities ID
Power Management Capabilities
Power Management Control/Status
Reserved
Software SMI
Reserved
ASL Storage
Default
Value
Access
—
—
—
07800000h
0000h
0001h
0022h
0000h
—
0000h
—
00000000h
—
RO
—
RO
RO
RO, R/W
—
R/W
—
R/W
10.1 Device 2 Function 1 Configuration Register Details
(D2:F1)
10.1.1
10.1.2
VID2—Vendor Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
00h
8086h
RO
16 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
DID2—Device Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
02h
2782h
RO
16 bits
This register is unique in Device 2, Function 1 (the Device 2, Function 0 DID is separate). This
difference in Device ID is necessary for allowing distinct Plug and Play enumeration of function 1
when both function 0 and function 1 have the same class code.
194
Datasheet