301467-005 Datasheet, PDF (48/426 Pages) Intel Corporation – Express Chipset

Signal Description
R
State During
State After
S3
Interface
Signal Name
I/O
RSTIN#
RSTIN# De-
Assertion
assertion
System
Channel B
Memory
(DDR2)
SCLK_B[5:0]
O
TRI
TRI
TRI
SCLK_B[5:0]#
O
TRI
TRI
TRI
SCS_B[3:0]#
O
TRI
TRI
TRI
SMA_B[13]
O
TRI
TRI
TRI
SMA_B[12:11]
O
LV
LV
LV
SMA_B[10:8]
O
TRI
TRI
TRI
O
LV
LV
LV
SMA_B[7]
O
TRI
TRI
TRI
SMA_B[6:0]
SBS_B[2]
O
LV
LV
LV
SBS_B[1:0]
O
TRI
TRI
TRI
SRAS_B#
O
TRI
TRI
TRI
SCAS_B#
O
TRI
TRI
TRI
SWE_B#
O
TRI
TRI
TRI
SDQ_B[63:0]
I/O
TRI
TRI
TRI
SDM_B[7:0]
O
TRI
TRI
TRI
SDQS_B[7:0]
I/O
TRI
TRI
TRI
SDQS_B[7:0]#
I/O
TRI
TRI
TRI
SCKE_B[3:0]
O
LV
LV
LV
SODT_B[3:0]
O
LV
LV
LV
SRCOMP0
I/O
TRI
TRI (after RCOMP)
TRI
SRCOMP1
I/O
TRI
TRI (after RCOMP)
TRI
SM_SLEWIN[1:0]
I
IN
IN
IN
SM_SLEWOU{1:0]
O
TRI
TRI (after RCOMP)
TRI
SMVREF[1:0]
I
IN
IN
IN
SOCOMP[1:0]
I/O
TRI
TRI
TRI
Pull-up/
Pull-down
DDR2: 40 Ω
resistor to
ground
48
Datasheet