301467-005 Datasheet, PDF (206/426 Pages) Intel Corporation – Express Chipset

System Address Map
R
⎯ IFPBAR – Any write to this window will trigger a flush of the (G)MCH’s Global Write
Buffer to let software guarantee coherency between writes from an isochronous agent
and writes from the processor (4-KB window).
⎯ GGC – 82915G/82915GV/82910GL GMCH graphics control register. Used to select the
amount of main memory that is pre-allocated to support the internal graphics device in
VGA (non-linear) and Native (linear) modes (0–64-MB options).
• Device 1: Function 0:
⎯ MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
⎯ PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
⎯ IOBASE1/IOLIMIT1 – PCI Express port I/O access window.
• Device 2: Function 0 (82915G/82915GV/82915GL/82910GL GMCH only)
⎯ MMADR – IGD registers and internal graphics instruction port. (512-KB window)
⎯ IOBAR – I/O access window for the GMCH internal graphics. Through this window
address/data register pair, using I/O semantics, the IGD and internal graphics instruction
port registers can be accessed. Note, this allows accessing the same registers as
MMADR. In addition, the IOBAR can be used to issue writes to the GTTADR table.
⎯ GMADR – Internal graphics translation window. (256-MB window)
⎯ GTTADR – Internal graphics translation table location. (256-KB window). Note that the
PGTBL_CTL register (MMIO 2020) indicates the physical address base which is 4 KB
aligned.
• Device 2: Function 1 (82915G/82915GV/82915GL/82910GL GMCH only)
⎯ MMADR – Function 1 IGD registers and internal graphics instruction port. (512-KB
window)
The rules for the above programmable ranges are:
• ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or system
designer’s responsibility to limit memory population so that adequate PCI, PCI Express, High
BIOS, PCI Express Memory Mapped space, and APIC memory space can be allocated.
• In the case of overlapping ranges with memory, the memory decode will be given priority.
• There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges.
• Accesses to overlapped ranges may produce indeterminate results.
• The only peer-to-peer cycles allowed below the top of memory (register TOLUD) are DMI to
PCI Express VGA range writes. Note that peer to peer cycles to the Internal Graphics VGA
range are not supported.
Figure 11-1 shows the system memory address map in a simplified form.
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Datasheet