301467-005 Datasheet, PDF (101/426 Pages) Intel Corporation – Express Chipset

MCHBAR Registers
R
5.1.8
C0BNKARC—Channel A DRAM Bank Architecture
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
10Eh
0000h
R/W
16 bits
This register is used to program the bank architecture for each Rank.
Bit
Access &
Default
15:8
Reserved
7:6
R/W
Rank 3 Bank Architecture
00b
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
5:4
R/W
Rank 2 Bank Architecture
00b
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
3:2
R/W
Rank 1 Bank Architecture
00b
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
1:0
R/W
Rank 0 Bank Architecture
00b
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
Description
Datasheet
101