301467-005 Datasheet, PDF (204/426 Pages) Intel Corporation – Express Chipset

Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.2
10.2.1
Device 2 – PCI I/O Registers
The following are not PCI configurations registers; they are I/O registers.
MMIO_INDEX—MMIO Address Register
I/O Address:
Size:
IOBAR + 0h
32 bits
MMIO_INDEX: A 32 bit I/O write to this port loads the offset of the memory-mapped I/O
(MMIO) register that needs to be accessed. An I/O Read returns the current value of this register.
An 8/16-bit I/O write to this register is completed by the GMCH but does not update this register.
This mechanism to access internal graphics MMIO registers must not be used to access VGA I/O
registers that are mapped through the MMIO space. VGA registers must be accessed directly
through the dedicated VGA IO ports.
Bit
Access &
Default
Description
31:2
R/W
Register Offset: This field selects any one of the DWord registers within the
00000000 h MMIO register space of Device 2.
1:0
Reserved
10.2.2
MMIO_DATA—MMIO Data Register
I/O Address:
Size:
IOBAR + 4h
32 bits
MMIO_DATA: A 32 bit I/O write to this port is re-directed to the MMIO register pointed to by
the MMIO-index register. A 32 bit I/O read to this port is re-directed to the MMIO register
pointed to by the MMIO-index register. 8 or 16 bit I/O writes are completed by the GMCH and
may have un-intended side effects; hence, they must not be used to access the data port. 8 or 16
bit I/O reads are completed normally.
Bit
Access &
Default
31:0
R/W
MMIO Data Window
00000000 h
Description
§
204
Datasheet