301467-005 Datasheet, PDF (224/426 Pages) Intel Corporation – Express Chipset

Functional Description
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12.1.3
APIC Cluster Mode Support
This is required for backwards compatibility with existing software, including various operating
systems. As one example, beginning with Microsoft Windows 2000 there is a mode (boot.ini) that
allows an end user to enable the use of cluster addressing support of the APIC.
The (G)MCH supports three types of interrupt re-direction:
• Physical
• Flat-Logical
• Clustered-Logical
12.2 System Memory Controller
This section describes the (G)MCH system memory interface for both DDR memory and DDR2
memory. The (G)MCH supports both DDR and DDR2 memory and either one or two DIMMs per
channel.
Note: The 82915G/82915GV GMCH and 82915P MCH support both DDR memory and DDR2
memory, and either one or two DIMMs per channel. The 82910GL only supports DDR memory
and a maximum of one DIMM per channel. The 82915PL and 82915GL support only DDR and
either one or two DIMMs per channel.
12.2.1
Memory Organization Modes
The system memory controller supports two styles of memory organization (Interleaved and
Asymmetric) and two modes of operation (DDR and DDR2). Rules for populating DIMM slots
are included in this chapter.
Interleaved Mode
This mode provides maximum performance on real applications. Addresses are ping-ponged
between the channels, and the switch happens after each cache line (64 byte boundary). If two
consecutive cache lines are requested, both may be retrieved simultaneously, since they are
guaranteed to be on opposite channels. The drawbacks of Interleaved Mode are that the system
designer must populate both channels of memory such that they have equal capacity, but the
technology and device width may vary from one channel to the other. Refer to Figure 12-1 for
further clarification.
Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode, addresses
start in channel A and stay there until the end of the highest rank in channel A; then, addresses
continue from the bottom of channel B to the top. Real world applications are unlikely to make
requests that alternate between addresses that sit on opposite channels with this memory
organization, so in most cases, bandwidth will be limited to that of a single channel. The system
designer is free to populate or not to populate any rank on either channel, including either
degenerate single channel case. Refer to Figure 12-1 for further clarification.
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