301467-005 Datasheet, PDF (246/426 Pages) Intel Corporation – Express Chipset

Functional Description
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12.6.7.3
Deinterlacing Support
For display on a progressive computer monitor, interlaced data that has been formatted for display
on interlaced monitors (TV) needs to be de-interlaced. The simple approaches to de-interlacing
create unwanted display artifacts. More advanced de-interlacing techniques have a large cost
associated with them. The compromise solution is to provide a low cost but effective solution and
enable both hardware and software based external solutions. Software based solutions are enabled
through a high bandwidth transfer to system memory and back.
Advanced Deinterlacing and Dynamic Bob and Weave
Interlaced data that originates from a video camera creates two fields that are temporally offset by
1/60 of a second. There are several schemes to deinterlace the video stream: line replication,
vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the
previous field and inserts them into the current field to construct the frame; this is known as
Weaving. This is the best solution for images with little motion however, showing a frame that
consists of the two fields will have serration or feathering of moving edges when there is motion
in the scene. Vertical filtering or “Bob” interpolates adjacent lines rather than replicating the
nearest neighbor. This is the best solution for images with motion; however, it will have reduced
spatial resolution in areas that have no motion and introduces aliasing. In the absence of any other
deinterlacing, these form the baseline and are supported by the GMCH.
Scaling Filter and Control
The scaling filter has three vertical taps and five horizontal taps. Arbitrary scaling (per pixel
granularity) for any video source (YUV422 or YUV420) format is supported.
The overlay logic can scale an input image up to 1600X1200with no major degradation in the
filter used as long as the maximum frequency limitation is met. Display resolution and refresh rate
combinations where the dot clock is greater than the maximum frequency require the overlay to
use pixel replication.
12.6.8
12.6.8.1
Pipes
The display consists of two pipes. The Pipes can operate in a single-wide or “double-wide” mode
at 2x graphics core clock though they are effectively limited by the respective display port. The
display planes and the cursor plane will provide a “double wide” mode to feed the pipe.
Clock Generator Units (DPLL)
The clock generator units provide a stable frequency for driving display devices. It operates by
converting an input reference frequency into an output frequency. The timing generators take
their input from internal DPLL devices that are programmable to generate pixel clocks in the
range of 25–400 MHz. Accuracy for VESA timing modes is required to be within ± 0.5%.
The DPLL can take a reference frequency from the external reference input (DREFCLKINN/P),
the TV clock input (TVCLKIN).
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Datasheet