301467-005 Datasheet, PDF (39/426 Pages) Intel Corporation – Express Chipset

Signal Description
R
2.3
Signal Name
SCKE_A[3:0]
SODT_A[3:0]
Type
O
SSTL-
2/1.8
O
SSTL-1.8
Description
Clock Enable: (1 per Rank) SACKE is used to initialize the SDRAMs
during power-up, to power-down SDRAM ranks, and to place all SDRAM
ranks into and out of self-refresh during Suspend-to-RAM.
On Die Termination (DDR2 only): Active On-die Termination Control
signals for DDR2 devices.
DDR/DDR2 DRAM Channel B Interface
Note that the 82910GL, 82915GL, and 82915PL (G)MCH only supports DDR DRAM.
Signal Name
SCLK_B[5:0]
SCLK_B[5:0]#
SCS_B[3:0]#
SMA_B[13:0]
SBS_B[2:0]
SRAS_B#
SCAS_B#
SWE_B#
SDQ_B[63:0]
SDM_B[7:0]
Type
O
SSTL-
2/1.8
O
SSTL-
2/1.8
O
SSTL-
2/1.8
O
SSTL-
2/1.8
O
SSTL-
2/1.8
O
SSTL-
2/1.8
O
SSTL-
2/1.8
O
SSTL-
2/1.8
I/O
SSTL-
2/1.8
2x
O
SSTL-
2/1.8
2x
Description
SDRAM Differential Clock: (3 per DIMM) SCLK_Bx and its complement
SCLK_Bx# signal make a differential clock pair output. The crossing of
the positive edge of SCLK_Bx and the negative edge of its complement
SCLK_Bx# are used to sample the command and control signals on the
SDRAM.
SDRAM Complementary Differential Clock: (3 per DIMM) These are
the complementary differential DDR/DDR2 clock signals.
Chip Select: (1 per Rank) These signals select particular SDRAM
components during the active state. There is one chip select for each
SDRAM rank
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM
Bank Select: These signals define which banks are selected within
each SDRAM rank
DDR2: 1-Gb technology is 8 banks.
DDR: 1-Gb technology is 4 banks. SBS_B[2] is not used
Row Address Strobe: This signal is used with SCAS_B# and SWE_B#
(along with SCS_B#) to define the SDRAM commands
Column Address Strobe: This signal is used with SRAS_B# and
SWE_B# (along with SCS_B#) to define the SDRAM commands.
Write Enable: This signal is used with SCAS_B# and SRAS_B# (along
with SCS_B#) to define the SDRAM commands.
Data Lines: SDQ_Bx signals interface to the SDRAM data bus
Data Mask: When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one SDM_Bx signal for
every data byte lane.
Datasheet
39