301467-005 Datasheet, PDF (193/426 Pages) Intel Corporation – Express Chipset

Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10 Device 2 Function 1 (D2:F1)
Configuration Registers
(Intel^® 82915G/82915GV/82915GL/
82910GL Only)
Table 10-1. Device 2 Function 1 Register Address Map Summary
Address
Offset
00–01h
02–03h
04–05h
06–07h
08h
Register
Symbol
VID2
DID2
PCICMD2
PCISTS2
RID2
Register Name
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
09–0Bh
0Ch
0Dh
0Eh
0Fh
10–13h
14–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
35–3Dh
3Eh
3Fh
40–43h
44h
45–47h
CC
CLS
MLT2
HDR2
—
MMADR
—
SVID2
SID2
ROMADR
CAPPOINT
—
MINGNT
MAXLAT
—
MCAPPTR
—
Class Code Register
Cache Line Size
Master Latency Timer
Header Type Register
Reserved
Memory Mapped Range Address
Reserved
Subsystem Vendor Identification
Subsystem Identification
Video BIOS ROM Base Address
Capabilities Pointer
Reserved
Minimum Grant Register
Maximum Latency
Reserved
Mirror of Dev0 Capability Pointer
Reserved
Default
Value
8086h
2780h
0000h
0090h
See register
description
03800h
00h
00h
80h
—
00000000h
—
0000h
0000h
00000000h
D0h
—
00h
00h
—
Access
RO
RO
RO, R/W
RO
RO
RO
RO
RO
RO
—
RO, R/W
—
R/WO
R/WO
RO
RO
—
RO
RO
—
—
—
Datasheet
193