301467-005 Datasheet, PDF (180/426 Pages) Intel Corporation – Express Chipset

Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.9
HDR2—Header Type (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
0Eh
80h
RO
8 bits
This register contains the Header Type of the IGD.
Bit
Access &
Default
Description
7
RO
Multi Function Status (MFunc): This bit indicates if the device is a Multi-
1b
Function Device. The Value of this register is determined by Device 0, offset 54h,
DEVEN[4]. If Device 0 DEVEN[4] is set, the Mfunc bit is also set.
6:0
RO
Header Code (H): This is a 7-bit value that indicates the Header Code for the
00h
IGD. This code has the value 00h, indicating a type 0 configuration space format.
9.1.10
MMADR—Memory Mapped Range Address (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
10h
00000000h
RO, R/W
32 bits
This register requests allocation for the IGD registers and instruction ports. The allocation is for
512 KB and the base address is defined by bits [31:19].
Bit
31:19
18:4
3
2:1
0
Access &
Default
R/W
0000h
RO
0000h
RO
0b
RO
00b
RO
0b
Description
Memory Base Address: Set by the OS, these bits correspond to address
signals [31:19].
Address Mask: Hardwired to 0s to indicate 512 KB address range.
Prefetchable Memory: Hardwired to 0 to prevent prefetching.
Memory Type: Hardwired to 0s to indicate 32-bit address.
Memory / IO Space: Hardwired to 0 to indicate memory space.
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Datasheet