301467-005 Datasheet, PDF (142/426 Pages) Intel Corporation – Express Chipset

Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.22
BCTRL1—Bridge Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
3Eh
0000h
RO, R/W
16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges.
The BCTRL provides additional control for the secondary interface (i.e., PCI Express) as well as
some bits that affect the overall behavior of the “virtual” Host-PCI Express bridge embedded
within (G)MCH (e.g., VGA compatible address ranges mapping).
Bit
15:12
11
10
9
8
7
6
5
4
3
Access &
Default
Description
Reserved
RO
Discard Timer SERR Enable: Hardwired to 0.
0b
RO
Discard Timer Status: Hardwired to 0.
0b
RO
Secondary Discard Timer: Hardwired to 0.
0b
RO
Primary Discard Timer: Hardwired to 0.
0b
RO
Fast Back-to-Back Enable (FB2BEN): Hardwired to 0.
0b
R/W
Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset on the
0b
corresponding PCI Express* Port.
RO
Master Abort Mode (MAMODE): When acting as a master, unclaimed reads
0b
that experience a master abort returns all 1s and any writes that experience a
master abort completes normally and the data is thrown away. Hardwired to 0.
R/W
VGA 16-bit Decode: This bit enables the PCI-to-PCI bridge to provide 16-bit
0b
decoding of VGA I/O address precluding the decoding of alias addresses every 1
KB. This bit only has meaning if bit 3 (VGA Enable) of this register is also set to
1, enabling VGA I/O decoding and forwarding by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
R/W
VGA Enable (VGAEN): This bit controls the routing of processor-initiated
0b
transactions targeting VGA compatible I/O and memory address ranges. See the
VGAEN/MDAP table in Device 0, offset 97h[0].
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Datasheet