301467-005 Datasheet, PDF (137/426 Pages) Intel Corporation – Express Chipset

Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.15
MBASE1—Memory Base Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
20h
FFF0h
R/W
16 bits
This register controls the processor to PCI Express Graphics non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes
when read. The configuration software must initialize this register. For the purpose of address
decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1-MB boundary.
Bit
Access &
Default
Description
15:4
R/W
Memory Address Base (MBASE): This field corresponds to A[31:20] of the
FFFh
lower limit of the memory range that will be passed to PCI Express*.
3:0
Reserved
Datasheet
137