301467-005 Datasheet, PDF (50/426 Pages) Intel Corporation – Express Chipset

Signal Description
R
Interface
Signal Name
I/O
State During
RSTIN#
Assertion
State After RSTIN#
De-assertion
S3
System
SWE_B#
O
TRI
TRI
TRI
Memory
(DDR)
SDQ_B[63:0]
I/O
TRI
TRI
TRI
SDM_B[7:0]
O
TRI
TRI
TRI
SDQS_B[7:0]
I/O
TRI
TRI
TRI
SDQS_B[7:0]#
I/O
TRI
TRI
TRI
SCKE_B[3:0]
O
LV
LV
LV
SRCOMP0
I/O
TRI
TRI (after RCOMP)
TRI
SRCOMP1
I/O
TRI
TRI (after RCOMP)
TRI
SM_SLEWIN[1:0]
I
IN
IN
IN
SM_SLEWOU[1:0]
O
TRI
TRI (after RCOMP)
TRI
SMVREF[1:0]
I
IN
IN
IN
SOCOMP[1:0]
I/O
TRI
TRI
TRI
Pull-up/
Pull-down
DDR2: 40 Ω
resistor to
ground
Table 2-4. PCI Express* Graphics x16 Port Reset and S3 States
Interface
Signal Name
PCI
Express*-
Graphics
EXP_RXN[15:0]
EXP_RXP[15:0]
EXP_TXN[15:0]
EXP_TXP[15:0]
EXP_COMPO
EXP_COMPI
I/O
State During
RSTIN#
Assertion
State After RSTIN#
De-assertion
I/O
CMCT
CMCT
I/O
CMCT
CMCT
O
CMCT 1.0 V
CMCT 1.0 V
O
CMCT 1.0 V
CMCT 1.0 V
I
TRI
TRI (after RCOMP)
I
TRI
TRI (after RCOMP)
S3
CMCT
CMCT
CMCT 1.0 V
CMCT 1.0 V
TRI
TRI
Pull-up/
Pull-down
Table 2-5. DMI Reset and S3 States
Interface
Signal Name
DMI
DMI_RXN[3:0]
DMI_RXP[3:0]
DMI_TXN[3:0]
DMI_TXP[3:0]
I/O
State During
RSTIN#
Assertion
State After RSTIN#
De-assertion
I/O
CMCT
I/O
CMCT
O
CMCT 1.0 V
O
CMCT 1.0 V
CMCT
CMCT
CMCT 1.0 V
CMCT 1.0 V
S3
CMCT
CMCT
CMCT 1.0 V
CMCT 1.0 V
Pull-up/ Pull-
down
50
Datasheet