301467-005 Datasheet, PDF (218/426 Pages) Intel Corporation – Express Chipset

System Address Map
R
11.4.3 SMM Space Combinations
When High SMM is enabled, the Compatible SMM space is effectively disabled. Processor
originated accesses to the Compatible SMM space are forwarded to PCI Express if this VGA
capability is enabled; otherwise, they are forwarded to the DMI. PCI Express and DMI originated
accesses are never allowed to access SMM space.
Table 11-5. SMM Space Table
Global Enable
G_SMRAME
0
1
1
1
1
High Enable
H_SMRAM_EN
X
0
0
1
1
TSEG Enable
TSEG_EN
X
0
1
0
1
Compatible
(C) Range
Disable
Enable
Enable
Disabled
Disabled
High (H)
Range
Disable
Disable
Disable
Enable
Enable
TSEG (T)
Range
Disable
Disable
Enable
Disable
Enable
11.4.4 SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows
software to write to the SMM ranges without being in SMM mode. BIOS software can use this bit
to initialize SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM
mode accesses. The D_CLS bit causes SMM data accesses to be forwarded to the DMI or PCI
Express. The SMM software can use this bit to write to video memory while running SMM code
out of DRAM.
Table 11-6. SMM Control Table
G_SMRAME D_LCK
0
x
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
D_CLS
X
X
0
0
1
1
X
0
1
D_OPEN
x
0
0
1
0
1
x
x
x
Processor in
SMM Mode
x
0
1
x
1
x
0
1
1
SMM Code
Access
Disable
Disable
Enable
Enable
Enable
Invalid
Disable
Enable
Enable
SMM Data
Access
Disable
Disable
Enable
Enable
Disable
Invalid
Disable
Enable
Disable
218
Datasheet