301467-005 Datasheet, PDF (113/426 Pages) Intel Corporation – Express Chipset

EPBAR Registers—Egress Port Register Summary
R
6.1.5
EPLE2A—EP Link Entry 2 Address
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
EPBAR
068h
0000000000008000h
RO
64 bits
This register provides the second part of a Link Entry that declares an internal link to another
Root Complex Element.
Bit
63:28
27:20
19:15
14:12
11:0
Access &
Default
RO
00h
RO
0 0001b
RO
000b
Description
Reserved
Bus Number
Device Number: Target for this link is PCI Express* x16 port (Device 1).
Function Number
Reserved
§
Datasheet
113