301467-005 Datasheet, PDF (82/426 Pages) Intel Corporation – Express Chipset

Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.19
PAM1—Programmable Attribute Map 1 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
91h
00h
R/W
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h–
0C7FFFh.
Bit Access &
Default
Description
7:6
Reserved
5:4
R/W
0C4000-0C7FFF Attribute (HIENABLE): This field controls the steering of read and
00b
write cycles that address the BIOS area from 0C4000h to 0C7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
3:2
Reserved
1:0
R/W
0C0000-0C3FFF Attribute (LOENABLE): This field controls the steering of read
00b
and write cycles that address the BIOS area from 0C0000h to 0C3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
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Datasheet