301467-005 Datasheet, PDF (198/426 Pages) Intel Corporation – Express Chipset

Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.8
MLT2—Master Latency Timer (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
0Dh
00h
RO
8 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.9
HDR2—Header Type Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
0Eh
80h
RO
8 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.10
MMADR—Memory Mapped Range Address (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
10h
00000000h
RO, R/W
32 bits
This register requests allocation for the IGD registers and instruction ports. The allocation is for
512 KB and the base address is defined by bits [31:19].
Bit
31:19
18:4
3
2:1
0
Access &
Default
R/W
0000h
RO
0000h
RO
0b
RO
00b
RO
0b
Description
Memory Base Address: Set by the OS, these bits correspond to address
signals [31:19].
Address Mask: Hardwired to 0s to indicate 512-KB address range.
Prefetchable Memory: Hardwired to 0 to prevent prefetching.
Memory Type: Hardwired to 0s to indicate 32-bit address.
Memory / IO Space: Hardwired to 0 to indicate memory space.
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Datasheet