301467-005 Datasheet, PDF (108/426 Pages) Intel Corporation – Express Chipset

MCHBAR Registers
R
5.1.21
PMCFG—Power Management Configuration
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
F10h
00000000h
R/W
32 bits
Bit
Access &
Default
Description
31:5
Reserved
4
R/W
Enhanced Power Management Features Enable
0b
0 = Legacy power management mode
1 = Reserved.
3:0
Reserved
5.1.22
PMSTS—Power Management Status
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
F14h
00000000h
R/W
32 bits
This register is Reset by PWROK only.
Bit
Access &
Default
Description
31:2
Reserved
1
R/WC/S Channel B in self-refresh. This bit is set by power management hardware after
0b
Channel B is placed in self refresh as a result of a Power State or a Reset Warn
sequence. It is cleared by power management hardware before starting Channel
B self refresh exit sequence initiated by a power management exit. It is cleared
by BIOS in a warm reset (Reset# asserted while pwrok is asserted) exit
sequence.
0 = Channel B not guaranteed to be in self-refresh.
1 = Channel B in Self-Refresh.
0
R/WC/S Channel A in Self-refresh. Set by power management hardware after Channel
0b
A is placed in self refresh as a result of a Power State or a Reset Warn
sequence. It is cleared by power management hardware before starting Channel
A self refresh exit sequence initiated by a power management exit. It is cleared
by the BIOS in a warm reset (Reset# asserted while PWOK is asserted) exit
sequence.
0 = Channel A not guaranteed to be in self-refresh.
1 = Channel A in Self-Refresh.
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Datasheet