301467-005 Datasheet, PDF (122/426 Pages) Intel Corporation – Express Chipset

DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7.1.11
DMILCAP—DMI Link Capabilities
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
084h
00012C41h
R/WO, RO
32 bits
This register indicates DMI specific capabilities.
Bit
31:18
17:15
14:12
11:10
9:4
3:0
Access &
Default
Description
R/WO
010b
R/WO
010b
RO
11b
RO
4h
RO
1h
Reserved
L1 Exit Latency (EL1). L1 not supported on DMI.
L0s Exit Latency (EL0): This field indicates that exit latency is 128 ns to less
than 256 ns.
Active State Link PM Support (APMS): This field indicates that L0s is supported
on DMI.
Maximum Link Width (MLW): This field indicates the maximum link width is
4 ports.
Maximum Link Speed (MLS): This field indicates the link speed is 2.5 Gb/s.
7.1.12
DMILCTL—DMI Link Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
088h
0000h
R/W
16 bits
This register allows control of DMI.
Bit
Access &
Default
Description
15:8
Reserved
7
R/W
Extended Synch (ES):
0h
1 = Forces extended transmission of FTS ordered sets when exiting L0s prior to
entering L0 and extra TS1 sequences at exit from L1 prior to entering L0.
6:2
Reserved
1:0
R/W
Active State Link PM Control (APMC): Indicates whether DMI should enter L0s.
00b
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
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