301467-005 Datasheet, PDF (66/426 Pages) Intel Corporation – Express Chipset

Host Bridge/DRAM Controller Registers (D0:F0)
R
Address
Offset
52–53h
54–57h
58–8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98–9Bh
9Ch
9Dh
Register
Symbol
GGC
DEVEN
—
PAM0
PAM1
PAM2
PAM3
PAM4
PAM5
PAM6
LAC
—
TOLUD
SMRAM
Register Name
GMCH Graphics Control Register (82915G
GMCH only)
Device Enable
Reserved
Programmable Attribute Map 0
Programmable Attribute Map 1
Programmable Attribute Map 2
Programmable Attribute Map 3
Programmable Attribute Map 4
Programmable Attribute Map 5
Programmable Attribute Map 6
Legacy Access Control
Reserved
Top of Low Usable DRAM
System Management RAM Control
Default
Value
0030h
00000019h
—
00h
00h
00h
00h
00h
00h
00h
00h
—
08h
00h
9Eh
ESMRAMC Extended System Management RAM Control
00h
9F–C7h
C8–C9h
—
ERRSTS
Reserved
Error Status
—
0000h
CA–CBh
CC–DBh
DC–DFh
E0–E8h
E9–FFh
100h
101h
102h
103h
104–107h
108h
109h
10A–10Bh
10Ch
10Dh
ERRCMD
—
SKPD
CAPID0
Error Command
Reserved
Scratchpad Data
Capability Identifier
—
C0DRB0
C0DRB1
C0DRB2
C0DRB3
—
C0DRA0
C0DRA2
—
C0DCLKDIS
—
Reserved
Channel A DRAM Rank Boundary Address 0
Channel A DRAM Rank Boundary Address 1
Channel A DRAM Rank Boundary Address 2
Channel A DRAM Rank Boundary Address 3
Reserved
Channel A DRAM Rank 0,1 Attribute
Channel A DRAM Rank 2,3 Attribute
Reserved
Channel A DRAM Clock Disable
Reserved
0000h
—
00000000h
0000000000
01090009h
—
00h
00h
00h
00h
—
00h
00h
—
00h
—
Access
R/W/L
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RO,
R/W/L
RO,
R/W/L
—
RO,
R/W/L
R/W
—
R/W
RO
—
R/W
R/W
R/W
R/W
—
R/W
R/W
—
R/W
—
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Datasheet