301467-005 Datasheet, PDF (191/426 Pages) Intel Corporation – Express Chipset

Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.31
SWSMI—Software SMI (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
E0h
0000h
R/W
16 bits
As long as there is the potential that DVO port legacy drivers exist that expect this register at this
address, Dev2, F0, address E0h–E1h must be reserved for this register.
Bit
Access &
Default
Description
15:8
R/W
SW scratch bits
00h
7:1
R/W
Software Flag: This field is used to indicate caller and SMI function desired, as
00h
well as return result.
0
R/W
GMCH Software SMI Event: When Set, this bit will trigger an SMI. Software
0b
must write a 0 to clear this bit
9.1.32
ASLE—System Display Event Register (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
2
E4h
00000000h
R/W
32 bits
Byte, Word, or Double Word PCI configuration cycles can access this register.
Bit
31:8
23:16
15:8
7:0
Access &
Default
R/W
00h
R/W
00h
R/W
00h
R/W
00h
Description
ASLE Scratch Trigger 3: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
ASLE Scratch Trigger 2: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
ASLE Scratch Trigger 1: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
ASLE Scratch Trigger 0: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
Datasheet
191