MC68HC08AZ32A Datasheet, PDF (97/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

IRQ Module During Break Interrupts
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected
by the IMASK bit, which makes it useful in applications where polling is preferred.
The BIH or BIL instruction is used to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
7.5 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ interrupt latch can be cleared during the
break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the
latches during the break state. See 15.7.3 SIM Break Flag Control Register (SBFCR).
To allow software to clear the IRQ latch during a break interrupt, write a 1 to the BCFE bit. If a latch is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
writing to the ACK bit in the IRQ status and control register during the break state has no effect on the
IRQ latch.
7.6 IRQ Status and Control Register (ISCR)
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR
performs the following functions:
• Indicates the state of the IRQ interrupt flag
• Clears the IRQ interrupt latch
• Masks IRQ interrupt requests
• Controls triggering sensitivity of the IRQ interrupt pin
Address:
Read:
Write:
Reset:
$001A
Bit 7
0
0
6
5
0
0
0
0
= Unimplemented
4
3
2
1
Bit 0
0
IRQF
0
IMASK MODE
ACK
0
0
0
0
0
Figure 7-5. IRQ Status and Control Register (ISCR)
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0. Reset clears ACK.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
97